The present invention relates to integrated circuit devices as well as to methods for personalizing and programming such devices, methods for finding faulty logic in integrated circuit devices and apparatus and techniques for the design and manufacture of semiconductor devices.
Various types of customizable integrated circuits and programmable integrated circuits are known in the art. Customizable integrated circuits include gate arrays, such as laser programmable gate arrays, commonly known as LPGA devices, which are described, inter alia in the following U.S. Pat. Nos. 4,924,287; 4,960,729; 4,933,738; 5,111,273; 5,260,597; 5,329,152; 5,565,758; 5,619,062; 5,679,967; 5,684,412; 5,751,165; 5,818,728. Devices of this type are customized by etching or laser ablation of metal portions thereof.
There are also known field programmable gate arrays, commonly known as FPGA devices, programmable logic devices, commonly known as PLD devices, as well as complex programmable logic devices, commonly known as CPLD devices. Devices of these types are programmable by application of electrical signals thereto.
It has been appreciated in the prior art that due to the relatively high silicon real estate requirements of FPGA devices, they are not suitable for many high volume applications. It has therefore been proposed to design functional equivalents to specific programmed FPGA circuits. Such functional equivalents have been implemented in certain cases using conventional gate arrays. The following U.S. Pat. Nos. show such implementations: U.S. Pat. Nos. 5,068,063; 5,526,278 and 5,550,839. 
Programmable logic devices are known in which programmable look up tables are employed to perform relatively elementary logic functions. Examples of such devices appear in U.S. Pat. Nos. 3,473,160 and 4,706,216. Multiplexers are also known to be used as programmable logic elements. Examples of such devices appear in U.S. Pat. Nos. 4,910,417, 5,341,041 and 5,781,033. U.S. Pat. Nos. 5,684,412, 5,751,165 and 5,861,641 show the use of multiplexers to perform customizable logic functions.
Problems of clock skew in gate arrays are well known. U.S. Pat. No. 5,420,544 describes a technique for reducing clock skew in gate arrays which employs a plurality of phase adjusting devices for adjusting the phase at various locations in gate arrays. Various clock tree design structures have been proposed which produce relatively low clock skew.
PCT Published Patent Application WO 98/43353 describes a functional block, architecture for a gate array.
U.S. Pat. Nos. 5,825,202 and 5,959,466 describes an integrated semiconductor device comprising a FPGA portion connected to a mask-defined application specific logic area.
Various types of gate arrays are well known in the art. Gate arrays comprise a multiplicity of transistors, which are prefabricated. A specific application is achieved by customizing interconnections between the transistors.
Routing arrangements have been proposed for reducing the number of custom masks and the time needed to manufacture gate arrays by prefabricating some of the interconnection layers in two-metal layer gate array devices. Prior art devices of this type typically employ three custom masks, one each for the first metal layer, via layer and second metal layer.
U.S. Pat. No. 4,197,555 to Uehara describes a two-metal layer gate array device wherein the first and second metal layers are pre-fabricated and the via layer is customized. Uehara also shows use of pre-fabricated first metal and via layers and customization of the second metal layer.
U.S. Pat. Nos. 4,933,738; 5,260,597 and 5,049,969 describe a gate array which, is customized by forming links in one or two prefabricated metal layers of a two-metal layer device.
U.S. Pat. No. 5,404,033 shows customization of a second metal layer of a two-metal layer device.
U.S. Pat. No. 5,581,098 describes a gate array routing structure for a two-metal layer device wherein only the via layer and the second metal layer are customized by the use of a mask.
Dual mode usage of Look-Up-Table SRAM cell to provide either a logic function or memory function has been proposed for FPGA devices in U.S. Pat. Nos. 5,801,547, 5,432,719 and 5,343,403.
Programmable and customizable logic arrays, such as gate arrays, are well known and commercially available in various sizes and at various levels of complexity. Recently cores of such logic arrays have become available.
Conventionally, cores are provided by a vendor based on customer""s specifications of gate capacity, numbers of input/output interfaces and aspect ratio. Each core is typically compiled by the vendor for the individual customer order. Even though the cores employ modular components, the compilation of the cores requires skilled technical support and is a source of possible errors.
Examples of prior art proposals which are relevant to this technology include Laser-programmable System Chips (LPSC), commercially available from Lucent Technologies Inc., and Programmable Logic Device (PLD) cores, commercially available from Integrated Circuit Technology Corp. of California.
Integrated circuits are prone to errors. The errors may originate in the design of an integrated circuit in a logically incorrect manner, or from faulty implementation.
A debugging process is required to detect these errors but fault-finding is a difficult process in integrated circuit devices due to the inaccessibility of the individual gates and logic blocks within the integrated circuit device.
The designer needs an apparatus and method for observing the behavior of an integrated circuit device, while the device is in its xe2x80x9cworking environmentxe2x80x9d. Furthermore, in order to isolate and determine a faulty area or section of an integrated circuit device, a designer needs to be able to control the inputs to the faulty area or section (controllability), and also to be able to observe the output from the faulty area (observability). In a typical integrated circuit device, controllability and observability are severely limited due to the inaccessibility of the device and the sequential nature of the logic.
The prior art teaches methods for enhancing the controllability and the observability of an integrated circuit device. A method suggested by Eichelberger et al., in xe2x80x9cA Logic Design Structure for LSI Testabilityxe2x80x9d, Proceeding of the 14th Design Automation Conference, June 1977, is to use a xe2x80x9cscan chainxe2x80x9d method. In this method of Eichelberger, storage elements are tied together in one or more chains. Each of these chains is tied to a primary integrated circuit pin. Special test clocks allow arbitrary data to be entered and scanned in the storage elements independent of the device""s normal function.
The following US patents are believed to represent the current state of the art: U.S. Pat. Nos. 5,179,534; 5,157,627, and 5,495,486.
Semiconductor devices, such as ASICs, have traditionally been manufactured by ASIC design and fabrication houses having both ASIC design and fabrication capabilities. Recently, however, the design and fabrication functionalities have become bifurcated, such that a customer may bring his fab-ready design to a fabrication house, having no design capability. The customer may employ conventionally available cell libraries, such as those available, for example, from Artisan or Mentor Graphics together with known design rules, to design their own devices.
Semiconductor design modules having specific functions, known as cores, are also available for integration by a customer into his design. An example of a commercially available core is a CPU core, commercially available from ARM Ltd. of Cambridge, England.
Cores may be provided in a variety of forms. For example, a xe2x80x9csoft corexe2x80x9d may be in the form of a high level schematic, termed RTL, while a xe2x80x9chard corexe2x80x9d may be at a layout level and be designed to specific fabrication design rules.
Conventional ASIC design flow is based on the use of synthesis software that assists a design-engineer to convert the design from high-level description code (RTL) to the level of gate netlist. Such a software tool is available from Synopsys Inc., 700 E. Middlefield, Mountain View, Calif., USA, and commercially available under the name of xe2x80x9cDesign Compilerxe2x80x9d. While software tools, such as xe2x80x9cDesign Compilerxe2x80x9d are highly complex, they are limited by, for example, the number of logic functions, called xe2x80x9cLibrary Functionsxe2x80x9d, which may be used for gate level implementation.
For example, xe2x80x9cDesign Compilerxe2x80x9d can use up to about 1,000 logic functions. This relatively small number of logic functions limits the usefulness of xe2x80x9cDesign Compilerxe2x80x9d with eCells. The term xe2x80x9ceCellxe2x80x9d is defined hereinbelow. A typical eCell may be configured to perform more than 32,000 different logic functions.
Therefore there is a necessity in the art to provide a tool for synthesizing an eCell.
The present invention seeks to provide an improved integrated circuit which, contrary to the teachings of the prior art, is both Customizable and programmable, and an improved integrated circuit which employs look up tables to provide highly efficient logic cells and logic functionalities.
Additionally, the present invention seeks to provide a multiple layer interconnection structure for a gate array device which has significant advantages over prior art structures, and employs at least three metal interconnection layers. customization is preferably realized by customization of a via layer and a layer overlying that via layer. Furthermore, the present invention seeks to provide a truly modular logic array to be used as core and to be embedded in a system-on-chip (SoC), which is composed of a combination of identical modular logic array units which are arranged in a desired mutual arrangement without the requirement of compilation.
The following terms, which are used in the present specification and claims, are defined as follows:
xe2x80x9ceCellxe2x80x9d is the building block of a configurable logic cell array. Typically, it is equivalent to about 15 ASIC logic gates.
xe2x80x9ceUnitxe2x80x9d is the structure of an array of 16xc3x9716 eCells with additional circuitry to support dual-port RAM mode XDEC and YDEC.
xe2x80x9cRAWxe2x80x9d is a structure of 16 eCells within an eUnit of cells, which include a line-type structure that is parallel to the XDEC.
xe2x80x9cCK-treexe2x80x9d or xe2x80x9cClock-treexe2x80x9d is a metal connecting structure that spreads across the logic to deliver the clock signal to the Flip/Flops (F/Fs) within that logic.
xe2x80x9cxc2xd-eCorexe2x80x9d is an array of 2xc3x974 or 4xc3x972 eUnits with additional circuits to support a clock driver, scan driver and counter with the logic to support loading the LUT""s RAM for the set-up mode.
xe2x80x9ceCorexe2x80x9d is a structure comprising two xc2xd-eCores to provide an array of either 4xc3x974 eUnits or an array of 2xc3x978 eUnits.
The present invention also seeks to provide an apparatus and method for adding controllability to fault-finding and debugging of an integrated circuit device, and in particular to a Look-Up-Table (LUT) logic device, without any change to the rest of the circuit. LUT units are used in many FPGA devices and also used in eASIC core devices, such as those of eASIC of San Jose, Calif., USA, and described in U.S. patent applications Ser. Nos. 09/265,998 and 09/310,962. Adding controllability to a RAM based LUT logic allows the debugging of integrated circuit devices within the working environment of the device. Although the present invention is described with respect to a 2-bit LUT, it is appreciated that the present method is also applicable to 3-bit, 4-bit and even larger LUT devices.
Additionally, the present invention seeks to provide a method for automatic distribution and licensing of semiconductor device cores, particularly xe2x80x9chard coresxe2x80x9d, as well as a modifiable core particularly suitable for use in the method. As the price,of tooling and manufacturing such S.O.C.""s is rapidly growing, and may be expected to exceed the $1 m mark for a 0.12 micron process, it is desirable to share and spread the costs of tooling among several customers. Thus, in accordance with yet another preferred embodiment of the present invention, the method for designing and manufacturing semiconductors may also involve an entity which provides the various services and resources required by a customer to design a required S.O.C. In the present specification and claims, the entity which provides this service is termed a xe2x80x9cVirtual ASICxe2x80x9d entity.
An effective way for organizing this service is for the Virtual ASIC entity to collect many different S.O.C. designs, which have been developed by other companies and include a wide range of previously built-in options. Each entry into the library or data bank, includes the S.O.C. identification in addition to the identification of the individual core included in it. The Virtual ASIC entity would then store all the information in a data bank or library and make it available to different customers.
A customer wishing to design an S.O.C., chooses a device, from the data bank, which is similar to his design requirements. The customer finalizes his own S.O.C. design based on the device design and data stored in the library. A completed S.O.C. design bears the S.O.C. identification, in addition to the identification of the individual core included in it. On completing the design of the S.O.C., the customer may update the data bank held by the Virtual ASIC entity with his S.O.C. design and data.
As described hereinabove, these design S.O.C.""s may include dedicated computerized functionalities, such as processors, DSP, and programmable and/or customizable logic.
Using various methods, adding mask tags, a Virtual ASIC entity may calculate the costs for NRE and production which may result from the wafer costs, the royalty obligations due to the various bodies which provided the cores, and due to the S.O.C. integrator as well as the other service and customization charges.
Thus, the customer is now able to review the technical capabilities of the chip, the required NRE and the production costs of his design. If the all the requirements of the customer are fulfilled, the customer can proceed and order the chip.
It is appreciated that such a service may be provided over the Internet to a customer who wishes to implement his own application based on the similar S.O.C. devices which are stored in the data bank of the Virtual ASIC.
The customer may include his own software code for the processors and/or the DSP and program and/or customize the logic to meet his own particular needs and requirements.
There is thus provided in accordance with a preferred embodiment of the present invention a personalizable and programmable integrated circuit device including at least first and second programmable logic cells and at least one permanent electrical conductive path interconnecting the at least first and second programmable logic cells for personalization of the integrated circuit device, wherein the at least first and second programmable logic cells are programmable by the application of an electrical signal thereto.
Further in accordance with a preferred embodiment of the present invention the programmable logic cells include a programmable look-up table.
Still further in accordance with a preferred embodiment of the present invention the a personalizable and programmable integrated circuit device includes at least first and second metal layers and a via layer to provide connection between the first metal layer and the second metal layer and wherein at least one of the first metal, second metal and via layers includes a repeating pattern. Preferably, at least one of the first metal, second metal and via layers include a custom pattern.
There is provided in accordance with a preferred embodiment of the present invention an integrated circuit device including at least first, second and third metal layers and a first via layer to provide connection between the first metal layer and the second metal layer and a second via layer to provide connection between the second metal layer and the third metal layer and wherein at least the first metal and the second metal layer include a repeating pattern and wherein at least one of the first via, second via and third metal layers include a custom pattern.
There is provided in accordance with another preferred embodiment of the present invention an integrated circuit device including at least first, second and third metal layers and a first via layer to provide connection between the first metal layer and the second metal layer and a second via layer to provide connection between the second metal layer and the third metal layer and wherein at least the first metal and the third metal layer include a repeating pattern and wherein at least one of the first via, second via and third metal layers include a custom pattern.
Further in accordance with a preferred embodiment of the present invention the device also includes a fourth metal layer.
Still further in accordance with a preferred embodiment of the present invention the fourth metal layer includes a repeating pattern.
Additionally in accordance with a preferred embodiment of the present invention the fourth metal layer includes a repeating pattern.
Preferably, the custom pattern is a via layer.
Further in accordance with a preferred embodiment of the present invention the custom pattern is prepared with direct write e-beam lithography.
Still further in accordance with a preferred embodiment of the present invention the first metal layer repeating pattern includes strips extending generally in parallel to a first axis.
Further in accordance with a preferred embodiment of the present invention the third metal layer repeating pattern includes strips extending generally in parallel to a first axis.
Still further in accordance with a preferred embodiment of the present invention at least two vias of first via layer are overlying at least one of the strips connecting the strips to second metal layer.
Additionally in accordance with a preferred embodiment of the present invention the at least two vias are at a distance greater than 6 times than the distance between two adjacent the strips.
Further in accordance with a preferred embodiment of the present invention the strips are stepped strips and are in a band of generally equal length strips.
Still further in accordance with a preferred embodiment of the present invention at least two vias are in propinquity to a beginning and an end of the at least one of the strips.
There is also provided in accordance with a preferred embodiment of the present invention the semiconductor device includes a substrate, at least first, second and third metal layers are formed over the substrate, the second metal layer including a plurality of generally parallel bands extending parallel to a first axis, each band including a multiplicity of second metal layer strips extending perpendicular to the first axis and at least one via connecting at least one second metal layer strip with the first metal layer underlying the second metal layer.
Further in accordance with a preferred embodiment of the present invention the third metal layer includes at least one third metal layer strip extending generally perpendicular to the second metal layer strips and being connected thereto by a via.
Still further in accordance with a preferred embodiment of the present invention the third metal layer includes at least one third metal layer strip extending generally parallel to the second metal layer strips and connecting two coaxial second metal layer strips by vias.
Preferably, the first metal layer includes at least one first metal layer strip extending generally perpendicular to the second metal layer strips and is connected thereto by a via.
Additionally in accordance with a preferred embodiment of the present invention the semiconductor device also includes at least one third metal layer strip extending parallel to the second metal layer strip and connecting two coaxial second metal layer strips.
Further in accordance with a preferred embodiment of the present invention the via includes a repeating pattern of vias.
Further in accordance with a preferred embodiment of the present invention the semiconductor device further includes relatively short second metal layer strips extending parallel to the first axis and located between the bands.
Still further in accordance with a preferred embodiment of the present invention the semiconductor device also includes at least one third metal layer strip extending parallel to the second metal layer strip and connecting two coaxial second metal layer strips.
Further in accordance with a preferred embodiment of the present invention the semiconductor device further includes a custom via layer connecting at least one of the second metal layer strip to the third metal layer.
Preferably, the third metal layer is a custom layer.
There is further provided in accordance with yet another preferred embodiment of the present invention a semiconductor device including a substrate, at least first, second and third metal layers formed over the substrate, the first metal layer including a plurality of generally parallel bands extending parallel to a first axis, each band including a multiplicity of first metal layer strips extending perpendicular to the first axis and at least one via connecting at least one third metal layer strip with the second metal layer underlying the third metal layer.
Further in accordance with a preferred embodiment of the present invention the second metal layer includes at least one second metal layer strip extending generally perpendicular to the first metal layer strips and being connected thereto by a via.
Still further in accordance with a preferred embodiment of the present invention the second metal layer includes at least one second metal layer strip extending generally parallel to the first metal layer strips and connecting two coaxial first metal layer strips by vias.
Additionally in accordance with a preferred embodiment of the present invention the third metal layer includes at least one third metal layer strip extending generally parallel to the first metal layer strips and having conductive path thereto.
Further in accordance with a preferred embodiment of the present invention the semiconductor device also includes at least one second metal layer strip extending parallel to the first metal layer strip and connecting two coaxial first metal layer strips.
Still further in accordance with a preferred embodiment of the present invention at least one via includes a repeating pattern of vias.
Additionally in accordance with a preferred embodiment of the present invention the semiconductor device further includes relatively short first metal strips extending parallel to the first axis and located between the bands.
Preferably, the semiconductor device further includes at least one second metal layer strip extending parallel to the first metal layer strip and connecting two coaxial first metal layer strips.
Further in accordance with a preferred embodiment of the present invention the semiconductor device also includes a custom via layer connecting at least one of the first metal layer strip to the second metal layer.
Still further in accordance with a preferred embodiment of the present invention the second metal layer is a custom layer.
There is further provided in accordance with a preferred embodiment of the present invention a method for the design and the manufacture of a semiconductor device. The method includes producing a fab-ready design for the semiconductor device by importing into the design at least one core for a remote source the core bearing an identification indicium, utilizing the fab-ready design to fabricate the semiconductor device and reading the identification indicium to indicate the preparation of the at least one core therein.
Further in accordance with a preferred embodiment of the present invention the importing step includes communication of the core via a communication link.
Still further in accordance with a preferred embodiment of the present invention the reading step is associated with a reporting step of the quantities of the core fabrication.
There is also provided in accordance with a preferred embodiment of the present invention a customizable and programmable integrated circuit device including at least first and second programmable logic cells, and at least two electrical conductive paths interconnecting the at least first and second programmable logic cells, at least a portion of which can be removed for customization of the integrated circuit device, wherein the at least first and second programmable logic cells are programmable by the application of an electrical signal thereto.
Further in accordance with a preferred embodiment of the present invention, at least one of the at least two conductive paths defines a short circuit between outputs of the at least first and second programmable logic cells.
Still further in accordance with a preferred embodiment of the present invention the integrated circuit device is integrated into a larger device.
Additionally in accordance with a preferred embodiment of the present invention at least a majority of the at least one of the at least two electrical conductive paths interconnecting the at least first and second programmable logic cells constitutes repeated subpatterns.
There is presented in accordance with yet another preferred embodiment of the present invention, a method for customization and programming of an integrated circuit device which includes providing an inoperative integrated circuit device, wherein the circuit device includes at least first and second programmable logic cells, and at least two electrical conductive paths interconnecting the at least first and second programmable logic cells, removing at least a portion of the at least two electrical conductive paths for customization of the integrated circuit devices, programming at least one of the at least first and second programmable logic cells by applying an electrical signal thereto, wherein the step of programming includes programming logic functions of the at least first and second programmable logic cells by the application of an electrical signal thereto.
There is also provided in accordance with a further preferred embodiment of the present invention a logic cell for use in a logic array, the logic cell includes at least one look-up table including a plurality of LUT inputs and at least one output, and at least one logic gate having a plurality of logic inputs and an output coupled to one of the plurality of LUT inputs.
Additionally in accordance with a preferred embodiment of the present invention a customizable and programmable integrated circuit device wherein at least a majority of the at least one interconnection path constitutes repeated subpatterns.
Further in accordance with a preferred embodiment of the present invention the logic cell also includes a multiplexer connected to an output of at least one look-up table and an inverter selectably connectable to at least one of an output of the multiplexer and an output of the look-up table.
Still further in accordance with a preferred embodiment of the present invention the logic cell also includes a metal interconnection layer overlying at least a portion of the cell for providing a custom interconnection between components thereof.
There is also provided in accordance with a preferred embodiment of the present invention a semiconductor device including a logic array including a multiplicity of identical logic cells, each identical logic cell comprising at least one look-up table, a metal connection layer overlying the multiplicity of identical logic cells for providing a permanent customized interconnect between various inputs and outputs thereof.
Further in accordance with a preferred embodiment of the present invention the logic cell comprises at least one multiplexer and the at least one look-up table provides an input to the at least one multiplexer.
Still further in accordance with a; preferred embodiment of the present invention, also including at least one logic gate connected to at least one input of the look-up table. Preferably at least one multiplexer is configured to perform a logic operation on the outputs from the at least one pair of look-up tables.
Additionally in accordance with a preferred embodiment of the present invention the look-up table is programmable.
Still further in accordance with a preferred embodiment of the present invention the logic cell includes at least one simple logic gate selectably connected to at least one logic cell output.
Moreover in accordance with a preferred embodiment of the present invention the logic array also includes a flip-flop for receiving an output from the multiplexer.
There is further provided in accordance with yet another preferred embodiment of the present invention a semiconductor device including a logic array comprising a multiplicity of identical logic cells, each identical logic cell including at least one flip-flop, and a metal connection layer overlying the multiplicity of identical logic cells for interconnecting various inputs and outputs thereof in a customized manner.
Further in accordance with a preferred embodiment of the present invention, the semiconductor device also includes a clock tree providing clock inputs to at least one of the at least one flip-flop of the multiplicity of identical logic cells.
Still further in accordance with a preferred embodiment of the present invention each logic cell receives a scan signal input which determines whether the cell operates in a normal operation mode or a test operation mode, wherein in a test operation mode nearly each flip-flop receives an input from an adjacent flip-flop thereby to define a scan chain.
Additionally in accordance with a preferred embodiment of the present invention the clock tree comprises a clock signal and an inverted clock signal.
There is further provided in accordance with yet another preferred embodiment of the present invention a semiconductor device including a substrate, at least first, second and third metal layers formed over the substrate, the second metal layer including a plurality of generally parallel bands extending parallel to a first axis, each band comprising a multiplicity of second metal layer strips extending perpendicular to the first axis, and at least one via connecting at least one second metal layer strip with the first metal layer underlying the second metal layer.
Further in accordance with a preferred embodiment of the present invention the third metal layer includes at least one third metal layer strip extending generally perpendicular to the second metal layer strips and being connected thereto by a via. Alternatively, the third metal layer includes at least one third metal layer strip extending generally parallel to the second metal layer strips and connecting two coaxial second metal layer strips by vias.
Still further in accordance with a preferred embodiment of the present invention the customizable logic core is customized for a specific application.
Additionally, the first metal layer comprises at least one first metal layer strip extending generally perpendicular to the second metal layer strips and being connected thereto by a via. Preferably the semiconductor device also includes at least one third metal layer strip extending parallel to the second metal layer strip and connecting two coaxial second metal layer strips.
Still further in accordance with a preferred embodiment of a semiconductor device the at least one via includes a repeating pattern of vias.
There is also provided in accordance with another preferred embodiment of the present invention a semiconductor device including a substrate, at least first, second, third and fourth metal layers formed over the substrate, the second metal layer comprising a plurality of generally parallel bands extending parallel to a first axis, each band comprising a multiplicity of long strips extending parallel to the first axis, the long strips including at least one of straight strips and stepped strips, at least one electrical connection between at least one strip in the second metal layer to the third metal layer, which overlies the second metal layer, and wherein the second metal layer includes a repeating pattern.
Further in accordance with a preferred embodiment of the present invention the strips of the second metal layer are connected to one of the third metal layer and the fourth metal layer, both of which overlie the second metal layer, by at least two electrical connections.
Still further in accordance with a preferred embodiment of the present invention the semiconductor device forms part of a larger semiconductor device.
Additionally in accordance with a preferred embodiment of the present invention the first metal layer comprises a plurality of generally parallel bands extending parallel to a first axis, each band comprising a multiplicity of long strips extending parallel to the first axis, the long strips including at least one of straight strips and stepped strips, at least one electrical connection between at least one strip in the first metal layer to the third metal layer, which overlies the first metal layer. Preferably the first metal layer comprises a repeating pattern.
There is provided in accordance with a preferred embodiment of the present invention an ASIC including at least one modular logic array which is constructed of a plurality of modular logic array units physically arranged with respect to each other to define a desired aspect ratio.
Further in accordance with a preferred embodiment of the present invention each modular logic array unit includes a generally circumferential border at which it is stitched onto any adjacent modular logic array unit.
Still further in accordance with a preferred embodiment of the present invention each logic array unit comprises between 10,000 and 200,000 gates.
Additionally in accordance with a preferred embodiment of the present invention each logic array unit has its own clock input.
There is further provided in accordance with a preferred embodiment of the present invention a data file for an ASIC which includes at least a reference to a plurality of identical modular data files, each corresponding to a logic array unit and data determining the physical arrangement of the logic units with respect to each other.
There is also provided in accordance with yet another preferred embodiment of the present invention a method for producing an ASIC including the step of providing a plurality of modular logic array units physically arranged with respect to each other to define a desired aspect ratio.
Further in accordance with a preferred embodiment of the present invention each modular logic array unit includes a generally circumferential border at which it is stitched onto any adjacent modular logic array unit.
Still further in accordance with a preferred embodiment of the present invention each logic array unit comprises between 10,000 and 200,000 gates.
There is also provided in accordance with another preferred embodiment of the present invention a method of producing a data file for an ASIC which includes the following steps combining without compiling together a plurality of identical modular data files, each corresponding to a logic array unit and data determining the physical arrangement of the logic units with respect to each other.
Further in accordance with a preferred embodiment of the present invention each logic array unit comprises between 10,000 and 200,000 gates.
Still further in accordance with a preferred embodiment of the present invention each logic array unit has its own clock input.
There is further provided in accordance with yet another preferred embodiment of the present invention a method of debugging an integrated circuit comprising logic gates in the form of look up tables, wherein each logic table comprises at least two data bits, the method includes modifying at least one of the data bits of one of the logic gates and examining the effect of the modification on an output of the integrated circuit without changing the routing. Preferably the modification is made into a high level language data file. Additionally or alternatively the high level language data file is used to modify a second data file corresponding to the data bits of at least some of the logic gates.
Furthermore the modified second data file as applied to at least some of the logic gates to modify at least some of the data bits thereof.
There is provided in accordance with yet another preferred embodiment of the present invention a method for fault detection of an Integrated Circuit (IC) including the steps of providing a first data file of a high level language with at least two signals defining a logic function, providing a second data file corresponding to the bit stream of a Look-Up-Table used to implement the logic function and modifying the second data file according to an user input signal to modify an output signal from the Look-Up-Table without changing the routing.
There is provided in accordance with another preferred embodiment of the present invention a method for design and manufacture of semiconductors including the steps of producing a fab-ready design for a semiconductor device by importing into the design at least one core from a remote source, the core bearing an identification indicium, utilizing the fab-ready design to fabricate the semiconductor device, and reading the identification indicium from the semiconductor device design to indicate incorporation of the at least one core therein.
Further in accordance with a preferred embodiment of the present invention the importing step includes communication of the core via the Internet.
Still further in accordance with a preferred embodiment of the present invention the reading step is associated with a reporting step which preferably includes reporting to an entity identified in the indicium data selected from the group consisting of the quantities of cores fabricated and the sizes the cores fabricated.
Preferably the producing step comprises interaction between a customer and a core provider""s web site.
Additionally in accordance with a preferred embodiment of the present invention the plurality of the devices are stored as a library. Preferably the identification indicium of each of the plurality of devices includes an identification code of the ownership of the device.
Moreover in accordance with a preferred embodiment of the present invention the devices include a programmable and customizable logic core.
There is also provided in accordance with a preferred embodiment of the present invention a semiconductor device including a plurality of pins, and customizable programmable logic containing a multiplicity of logic cells and a multiplicity of electrical connections between the multiplicity of logic cells, at least some of the multiplicity of logic cells being programmable by means of electrical signals supplied thereto via at least some of the plurality of pins, and at least some of the multiplicity of electrical connections being customized for a particular logic function by lithography carried out in the course of manufacture of the semiconductor device.
There is also provided in accordance with a preferred embodiment of the present invention, a method of producing a semiconductor device including a plurality of pins and customizable programmable logic containing a multiplicity of logic cells and a multiplicity of electrical connections between the multiplicity of logic cells, including the steps of defining, on a semiconductor substrate, a multiplicity of logic cells which are programmable by means of electrical signals supplied thereto via at least some of the plurality of pins, forming the multiplicity of electrical connections over the semiconductor substrate by lithography, and in the course of the forming step, customizing at least some of the multiplicity of electrical connections for a specific logic function by lithography.
Further in accordance with a preferred embodiment of the present invention, the method also includes the step of programming at least some of the multiplicity of logic cells by means of electrical signals supplied thereto via at least some of the plurality of pins.
There is further provided in accordance with yet another preferred embodiment of the present invention a method for recycling integrated circuit designs including the steps of providing an integrated circuit design including multiple design elements from a design proprietor, removing at least part of the multiple design elements from the integrated circuit design, supplying the integrated circuit design having removed therefrom the at least part of the multiple design elements to a design recipient, utilizing the integrated circuit design having removed therefrom the at least part of the multiple design elements by the design recipient to create a second integrated circuit design, providing compensation from the design recipient to the design proprietor for the use of the integrated circuit design having removed therefrom the at least part of the multiple design elements.
There is also provided in accordance with another preferred embodiment of the present invention, a method for distributing integrated circuit designs including the steps of causing a proprietor of integrated circuit designs to make them available to potential users for use and inspection, embedding in the integrated circuit designs identification information when enables an integrated circuit fab to identify the source of the designs in an integrated circuit fabricated on the basis thereof, causing the integrated circuit fab to identify the source of the integrated circuit designs using the identified information, and causing the integrated circuit fab to pay compensation to the proprietor based at least in part on identification of the integrated circuits.
There is provided in accordance with yet another preferred embodiment of the present invention an integrated circuit device including a semiconductor substrate defining a multiplicity of semiconductor elements, a plurality of metal layers formed over the semiconductor substrate by lithography, at least the semiconductor substrate being designed such that the functionality of the multiplicity of semiconductor elements as being either logic or memory is determined by the configuration of the plurality of metal layers.
Further in accordance with a preferred embodiment of the present invention the at least the semiconductor substrate is designed such that the functionality of the multiplicity of semiconductor elements as being either logic or memory is determined solely by the configuration of the plurality of metal layers.
There is also provided in accordance with yet another preferred embodiment of the present invention an integrated circuit device including a semiconductor substrate, and a plurality of metal layers formed over the semiconductor substrate and defining programmable logic including at least one ferroelectric element.
There is further provided in accordance with yet another preferred embodiment of the present invention an integrated circuit device including a semiconductor substrate, and a plurality of metal layers formed over the semiconductor substrate and being designed to enable routing connections including at least three metal layers to be customized by forming vias.
There is also provided in accordance with yet another preferred embodiment of the present invention a semiconductor device a plurality of pins and customizable programmable logic containing a multiplicity of logic cells and a multiplicity of electrical connections within the multiplicity of logic cells, at least some of the multiplicity of logic cells being programmable by means of electrical signals supplied thereto via at least some of the plurality of pins and by customization of the electrical connections.
Further in accordance with a preferred embodiment of the present invention a semiconductor device, which also includes a multiplicity of electrical connections between the multiplicity of logic cells, at least some of the multiplicity of electrical connections being customized for a particular logic function by lithography carried out in the course of manufacture of the semiconductor device.
There is also provided in accordance with yet another preferred embodiment of the present invention a semiconductor device including a plurality of look up tables, each having a look up table output, a multiplexer having a plurality of inputs receiving the look up table outputs of the plurality of look up tables, and a switch arranged in series between at least one of the look up table outputs and an input of the multiplexer, the switch enabling one of at least two of the following inputs to be supplied to the input of the multiplexer: logic zero, logic 1, and the output of the look up table.
Further in accordance with a preferred embodiment of the present invention, the semiconductor device and also includes a flip flop receiving an output of the multiplexer and wherein the switch enables one of at least two of the following inputs to be supplied to the input of the multiplexer: logic zero, logic 1, the output of the look up table and the output of the flip flop.
There is further provided in accordance with yet another preferred embodiment of the present invention a method of employing synthesis software for integrated circuit design including the steps of defining for the synthesis software a multiplicity of 2-input and 3-input logic functions, operating the synthesis software utilizing the multiplicity of 2-input and 3-input logic functions to provide a circuit design, mapping at least some of the logic functions for implementation by a multiplexer in a semiconductor device including a plurality of look up tables, each having a look up table output, a multiplexer having a plurality of inputs receiving the look up table outputs of the plurality of look up tables, and a switch arranged in series between at least one of the look up table outputs and an input of the multiplexer, the switch enabling one of at least two of the following inputs to be supplied to the input of the multiplexer: logic zero, logic 1, and the output of the look up table.
There is also provided in accordance with another preferred embodiment of the present invention a customizable and programmable integrated circuit including at least first and second programmable logic cells each having at least one input and at least one output, and at least one permanent interconnection path interconnecting at least one output of at least one of the first and second programmable logic cells with at least one input of at least one of the first and second programmable logic cells.
Further in accordance with a preferred embodiment of the present invention the at least first and second programmable logic cells are programmable by the application of an electrical signal thereto. Preferably the logic functions of the at least first and second programmable logic cells are programmable by the application of an electrical signal thereto.
Still further in accordance with a preferred embodiment of the present invention the at least one interconnection path defines a short circuit between outputs of the at least first and second programmable logic cells.
Additionally in accordance with a preferred embodiment of the present invention the integrated circuit device comprises a stand-alone device.
Moreover in accordance with a preferred embodiment of the present invention the integrated circuit device is integrated into a larger device.
There is further provided in accordance with a preferred embodiment of the present invention a customizable logic array device including an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs, and customized interconnections permanently interconnecting at least a plurality of the multiplicity of inputs and at least a plurality of the multiplicity of outputs.
There is also provided in accordance with a preferred embodiment of the present invention an array of field programmable gates having permanent customized connections.
Further in accordance with a preferred embodiment of the present invention the permanent customized connections are mask defined.
There is further provided in accordance with yet another preferred embodiment of the present invention a basic cell in a mask programmable gate array, the basic cell comprising at least one programmable logic cell.
Further in accordance with a preferred embodiment of the present invention the programmable logic cell comprises a Look-Up-Table. Preferably the Look-Up-Table comprises a mask programmable memory cell.
Still further in accordance with a preferred embodiment of the present invention the Look-Up-Table includes the following at least two inputs, and an electronic circuit which provides high speed response to changes in one of the two inputs with respect to the response time of changes to the other input.
Additionally in accordance with a preferred embodiment of the present invention the Look-Up-Table is programmed at least twice during a testing process.
There is thus provided in accordance with a preferred embodiment of the present invention a customizable and programmable integrated circuit device including: at least first and second programmable logic cells, and at least two electrical conductive paths interconnecting the at least first and second programmable logic cells, at least a portion of which can be removed for customization of the integrated circuit device.
There is additionally provided in accordance with a preferred embodiment of the present invention a customizable and programmable integrated circuit device including: at least first and second programmable logic cells, and at least one customizable electrical conductive path interconnecting the at least first and second programmable logic cells, the conductive path defining a short circuit between outputs of the at least first and second programmable logic cells.
There is further provided in accordance with a preferred embodiment of the present invention a selectably configurable and field programmable integrated circuit device including: at least first and second field programmable logic cells, and at least two electrical conductive paths interconnecting the at least first and second programmable logic cells, at least a portion of which can be removed for selectable configuration of the integrated circuit devices.
Preferably, the at least first and second programmable logic cells are programmable by the application of an electrical signal thereto.
In accordance with a preferred embodiment of the present invention, functions of the at least first and second programmable logic cells are programmable by the application of an electrical signal thereto and logic functions of the at least first and second programmable logic cells are programmable by the application of an electrical signal thereto.
Preferably at least one of the at least two conductive paths defines a short circuit between outputs of the at least first and second programmable logic cells.
There is also provided in accordance with a preferred embodiment of the present invention a selectably configurable and programmable integrated circuit device including: at least first and second programmable logic cells, and at least two selectably configurable electrical conductive paths interconnecting the at least first and second programmable logic cells, at least one of which defines a short circuit between outputs of the at least first and second programmable logic cells.
Preferably, the at least first and second programmable logic cells are programmable by the application of an electrical signal thereto.
In accordance with a preferred embodiment of the present invention, functions, preferably comprising logic functions, of the at least first and second programmable logic cells are programmable by the application of an electrical signal thereto.
Preferably, programming of the first and second programmable logic cells may take place following selectable configuration of the device.
There is additionally provided in accordance with a preferred embodiment of the present invention a selectably configurable and programmable integrated circuit device wherein programming of the first and second programmable logic cells may take place following selectable configuration of the device.
In accordance with a preferred embodiment of the present invention the first and second programmable logic cells may be reprogrammed.
There is also provided in accordance with a preferred embodiment of the present invention a method for customization and programming of an integrated circuit device including: providing an inoperative integrated circuit device including: at least first and second programmable logic cells, and at least one electrical conductive path interconnecting the at least first and second programmable logic cells, removing at least a portion of the electrical conductive path for customization of the integrated circuit devices.
Preferably, the method also includes the step of programming at least one of the at least first and second programmable logic cells by applying an electrical signal thereto.
In accordance with a preferred embodiment of the present invention, the step of programming includes programming functions, preferably including logic functions, of the at least first and second programmable logic cells by the application of an electrical signal thereto.
Preferably, the step of removing includes eliminating a short circuit between outputs of the at least first and second programmable logic cells by etching at least one conductive layer.
There is also provided in accordance with a preferred embodiment of the present invention a method for customization and programming of an integrated circuit device including: providing an inoperative integrated circuit device including at least first and second programmable logic cells, and at least two electrical conductive paths interconnecting the at least first and second programmable logic cells, removing at least a portion of the at least two electrical conductive paths for eliminating a short circuit between outputs of the at least first and second programmable logic cells.
There is additionally provided in accordance with a preferred embodiment of the present invention a method for selectable configuration and programming of an integrated circuit device including providing an inoperative integrated circuit device including at least first and second programmable logic cells, and at least two electrical conductive paths interconnecting the at least first and second programmable logic cells, removing at least a portion of the at least two electrical conductive paths for selectable configuration of the integrated circuit device.
There is further provided a method for selectable configuration and programming of an integrated circuit device including providing an inoperative integrated circuit device including at least first and second programmable logic cells, and at least two electrical conductive paths interconnecting the at least first and second programmable logic cells, and removing at least a portion of the at least two electrical conductive paths for eliminating a short circuit between outputs of the at least first and second programmable logic cells.
There is additionally provided in accordance with a preferred embodiment of the present invention a customizable and programmable integrated circuit device including: at least first and second programmable logic cells which are programmable by application thereto of an electrical signal, and at least two electrical conductive paths interconnecting the at least first and second programmable logic cells, at least a portion of which can be removed by etching for customization of the integrated circuit device.
There is further provided in accordance with a preferred embodiment of the present invention a customized programmable integrated circuit device including at least first and second programmable logic cells which are programmable by application thereto of an electrical signal, and at least two electrical conductive paths interconnecting the at least first and second programmable logic cells, at least a portion of which has been removed by etching during customization of the integrated circuit device.
It is appreciated that the integrated circuit device may comprise a conventional integrated circuit device having only a portion thereof constructed and operative in accordance with the present invention to be both customizable and programmable.
The present invention seeks to provide an improved integrated circuit which employs look up tables to provide highly efficient logic cells and logic functionalities.
There is thus provided in accordance with a preferred embodiment of the present invention a logic cell for use in a logic array, the logic cell including: at least one look-up table including a plurality of LUT inputs and at least one output, and at least one logic gate having a plurality of logic inputs and an output coupled to one of the plurality of LUT inputs.
According to one embodiment of the invention, the logic gate is a 2-input logic gate. According to an alternative embodiment of the invention, the logic gate is a NAND gate.
Preferably, the at least one look-up table includes at least one pair of look-up tables.
In accordance with a preferred embodiment of the invention, the logic cell also includes a multiplexer receiving outputs from the at least one pair of look-up tables.
In accordance with another preferred embodiment of the invention, the at least one look-up table includes first and second pairs of look-up tables, the logic cell also including first and second multiplexers, each multiplexer receiving outputs from a pair of look-up tables.
Preferably, the logic cell also includes a third multiplexer receiving outputs from the first and second multiplexers.
Additionally in accordance with a preferred embodiment of the present invention, the logic cell also includes a flip-flop for receiving an output from the first multiplexer.
In accordance with an alternative embodiment of the present invention, the logic cell also includes a multiplexer connected to an output of at least one look-up table and an inverter selectably connectable to at least one of an output of the multiplexer and an output of the look-up table.
The look-up table is preferably a programmable look-up table.
In accordance with a preferred embodiment of the present invention, the logic cell also includes a metal interconnection layer overlying at least a portion of the cell for providing a custom interconnection between components thereof.
There is also provided in accordance with a preferred embodiment of the present invention a semiconductor device including a logic array including a multiplicity of identical logic cells, each identical logic cell including at least one look-up table, a metal connection layer overlying the multiplicity of identical logic cells for providing a permanent customized interconnect between various inputs and outputs thereof.
Preferably each device includes at least one multiplexer and the at least one look-up table provides an input to the at least one multiplexer.
Additionally, each device preferably also includes at least one logic gate connected to at least one input of the look-up table.
According to one embodiment of the invention, the logic gate is a 2-input logic gate. According to an alternative embodiment of the invention, the logic gate is a NAND gate connected to an input of the at least one look-up table.
Preferably, the at least one look-up table includes at least one pair of look-up tables.
In accordance with a preferred embodiment of the present invention, the at least one multiplexer receives outputs from the at least one pair of look-up tables. Preferably, the at least one multiplexer is configured to perform a logic operation on the outputs from the at least one pair of look-up tables.
In accordance with an embodiment of the invention, the at least one look-up table includes first and second pairs of look-up tables and the at least one multiplexer includes first and second multiplexers, each multiplexer receiving outputs from a pair of look-up tables.
Preferably, the look-up table is programmable.
In accordance with a preferred embodiment of the present invention, the device includes at least one simple logic gate selectably connected to at least one logic cell output.
Preferably, the simple logic gate is a two-input logic gate. Alternatively it may be an inverter or a buffer.
The device preferably also includes a multiplexer connected to an output of at least one look-up table and an inverter selectably connectable to an output of the at least one multiplexer.
In accordance with a preferred embodiment of the present invention, the device also includes a metal interconnection layer overlying at least a portion of the cell for providing a custom interconnection between components thereof.
There is also provided in accordance with a preferred embodiment of the present invention a logic array including at least one logic cell, the logic cell including: at least one look-up table including a plurality of LUT inputs and at least one output, and at least one logic gate having a plurality of logic inputs and an output coupled to one of the plurality of LUT inputs.
The at least one look-up table is preferably a programmable look-up table.
According to one embodiment of the invention, the logic array is a 2-input logic gate. According to an alternative embodiment of the invention, the logic gate is a NAND gate.
Preferably, the at least one look-up table includes at least one pair of look-up tables.
In accordance with a preferred embodiment of the invention, the logic array also includes a multiplexer receiving outputs from the at least one pair of look-up tables.
In accordance with another preferred embodiment of the invention, the at least one look-up table includes first and second pairs of look-up tables, the logic cell also including first and second multiplexers, each multiplexer receiving outputs from a pair of look-up tables.
Preferably, the logic array also includes a third multiplexer receiving outputs from the first and second multiplexers.
Additionally in accordance with a preferred embodiment of the present invention, the logic array also includes a flip-flop for receiving an output from the first multiplexer.
In accordance with an alternative embodiment of the present invention, the logic array also includes a multiplexer connected to an output of at least one look-up table and an inverter selectably connectable to at least one of an output of the multiplexer and an output of the look-up table.
In accordance with a preferred embodiment of the present invention, the logic array also includes a metal interconnection layer overlying at least a portion of the cell for providing a custom interconnection between components thereof.
The logic array may be integrated into a larger device also formed on the same substrate.
There is additionally provided in accordance with a preferred embodiment of the present invention a semiconductor device including a logic array including a multiplicity of identical logic cells, each identical logic cell including at least one flip-flop, and a metal connection layer overlying the multiplicity of identical logic cells for interconnecting various inputs and outputs thereof in a customized manner.
The semiconductor device may also include a clock tree providing clock inputs to at least one of the at least one flip-flop of the multiplicity of identical logic cells.
Each logic cell in the semiconductor device may also receive a scan signal input which determines whether the cell operates in a normal operation mode or a test operation mode, wherein in a test operation mode nearly each flip-flop receives an input from an adjacent flip-flop thereby to define a scan chain.
The logic cell preferably includes a programmable look-up table.
The present invention seeks to provide a multiple layer interconnection structure for a gate array device which has significant advantages over prior art structures.
The present invention employs at least three metal interconnection layers. Customization is preferably realized by customization of a via layer and a layer overlying that via layer.
There is thus provided in accordance with a preferred embodiment of the present invention a semiconductor device including a substrate, at least first, second and third metal layers formed over the substrate, the second metal layer including a plurality of generally parallel bands extending parallel to a first axis, each band including a multiplicity of second metal layer strips extending perpendicular to the first axis, and at least one via connecting at least one second metal layer strip with the first metal layer underlying the second metal layer.
Preferably the at least one via includes a repeating pattern of vias.
Further in accordance with a preferred embodiment of the present invention the third metal layer includes at least one third metal layer strip extending generally perpendicular to the second metal layer strips and being connected thereto by a via.
Still further in accordance with a preferred embodiment of the present invention the third metal layer includes at least one third metal layer strip extending generally parallel to the second metal layer strips and connecting two coaxial second metal layer strips by vias.
Additionally in accordance with a preferred embodiment of the present invention the first metal layer underlying the second metal layer includes a multiplicity of first metal layer strips extending generally parallel to the multiplicity of second metal layer strips. Furthermore, at least one of the first metal layer strips is electrically connected at ends thereof to different second metal layer strips for providing electrical connection therebetween.
Further in accordance with a preferred embodiment of the present invention the second metal layer strips include both relatively long strips and relatively short strips, at least one of the relatively short strips being connected to the first metal layer by a via. Preferably the relatively short second metal layer strips are arranged in side by side arrangement. Alternatively the relatively short second metal layer strips are arranged in spaced coaxial arrangement.
Additionally or alternatively the third metal layer includes a bridge connecting adjacent pairs of the relatively short second metal layer strips.
Still further in accordance with a preferred embodiment of the present invention the third metal layer includes at least one third metal layer strip extending perpendicular to the second metal layer strips and being connected thereto by a via. Furthermore, the third metal layer includes at least one third metal layer strip extending parallel to the second metal layer strips and connecting two coaxial second metal layer strips by vias.
Additionally in accordance with a preferred embodiment of the present invention the first metal layer comprises at least one first metal layer strip extending generally perpendicular to the second metal layer strips and being connected thereto by a via. Preferably the third metal layer includes at least one third metal layer strip extending perpendicular to the second metal layer strips and being connected thereto by a via.
Moreover in accordance with a preferred embodiment of the present invention the first metal layer includes first metal layer strips extending generally perpendicular to the second metal layer strips, the first metal layer strips being electrically connected at ends thereof by the vias to the second relatively short metal layer strips.
Still further in accordance with a preferred embodiment of the present invention the third metal layer comprises at least one third metal layer strip extending parallel to the second metal layer strips and connecting two coaxial second metal layer strips by vias.
Additionally in accordance with a preferred embodiment of the present invention also including at least one third metal layer strip extending parallel to the second metal layer strip and connecting two coaxial second metal layer strips.
There is also provided in accordance with a preferred embodiment of the present invention a semiconductor device including a substrate, at least first, second and third metal layers formed over the substrate, the second metal layer including a multiplicity of second metal layer strips extending perpendicular to the first axis, adjacent ones of the second metal layer strips having ends which do not lie in a single line.
Further in accordance with a preferred embodiment of the present invention the second metal layer strips are interlaced with one another.
Still further in accordance with a preferred embodiment of the present invention the third metal layer includes at least one third metal layer strip extending generally perpendicular to the second metal layer strip and being connected thereto by a via.
Additionally in accordance with a preferred embodiment of the present invention the third metal layer includes at least one third metal layer strip extending generally parallel to the second metal layer strips and connecting two coaxial second metal layer strips by vias.
There is provided in accordance with yet another preferred embodiment of the present invention a semiconductor device including a substrate, at least first, second and third metal layers formed over the substrate, the second metal layer including a plurality of generally parallel bands extending parallel to a first axis, each band comprising a multiplicity of second metal layer strips extending perpendicular to the first axis, and a plurality of mutually parallel relatively short second metal layer strips extending generally parallel to the first axis.
Further in accordance with a preferred embodiment of the present invention the third metal layer includes at least one third metal layer strip extending generally perpendicular to the second metal layer strips and being connected thereto by a via. Preferably at least one of the third metal strips connects two second metal layer strips by means of vias.
Still further in accordance with a preferred embodiment of the present invention the third metal layer includes at least one third metal layer strip extending generally parallel to the second metal layer strips and connecting two coaxial second metal layer strips by vias. Preferably at least one of the third metal strips connects two second metal layer strips by means of vias.
Additionally in accordance with a preferred embodiment of the present invention including at least one via connecting at least one second metal layer strip with the first metal layer underlying the second metal layer.
There is provided in accordance with yet another preferred embodiment of the present invention a semiconductor device including a substrate, at least first, second, third and fourth metal layers formed over the substrate, the second metal layer including a plurality of generally parallel bands extending parallel to a first axis, each band comprising a multiplicity of long strips extending parallel to the first axis, the long strips including at least one of straight strips and stepped strips, at least one electrical connection between at least one strip in the second metal layer to the third metal layer, which overlies the second metal layer.
Preferably the second metal layer comprises a repeating pattern.
Further in accordance with a preferred embodiment of the present invention the strips of the second metal layer are connected to one of the third metal layer and the fourth metal layer, both of which overlie the second metal layer, by least two electrical connections.
Alternatively most of the strips of the second metal layer are connected to one of the third metal layer and the fourth metal layer, both of which overlie the second metal layer, by least two electrical connections.
Further in accordance with a preferred embodiment of the present invention at least one of the strips of the second metal layer is electrically connected to another one of the strips of the second metal layer which is non-adjacent thereto.
Preferably the device forms part of a larger semiconductor device.
Still further in accordance with a preferred embodiment of the present invention the first metal layer includes a plurality of generally parallel bands extending parallel to a first axis, each band comprising a multiplicity of long strips extending parallel to the first axis, the long strips including at least one of straight strips and stepped strips, and at least one electrical connection between at least one strip in the first metal layer to the third metal layer, which overlies the first metal layer.
Additionally in accordance with a preferred embodiment of the present invention the first metal layer includes a repeating pattern.
Further in accordance with a preferred embodiment of the present invention the strips of the first metal layer are connected to one of the third metal layer and the fourth metal layer, both of which overlie the first metal layer, by least two electrical connections.
Alternatively most of the strips of the first metal layer are connected to one of the third metal layer and the fourth metal layer, both of which overlie the first metal layer, by least two electrical connections.
Further in accordance with a preferred embodiment of the present invention at least one of the strips of the first metal layer is electrically connected to another one of the strips of the first metal layer which is non-adjacent thereto.
Additionally in accordance with a preferred embodiment of the present invention the semiconductor device forms part of a larger semiconductor device.
The present invention seeks to provide a truly modular logic array to be used as core and to be embedded in a system-on-chip, which is composed of a combination of identical modular logic array units which are arranged in a desired mutual arrangement without the requirement of compilation.
There is thus provided in accordance with a preferred embodiment of the present invention a modular logic array which is constructed of a plurality of modular logic array units physically arranged with respect to each other to define a desired aspect ratio.
There is also provided in accordance with a preferred embodiment of the present invention a data file for a modular logic array which comprises at least a reference to a plurality of identical modular data files, each corresponding to a logic array unit and data determining the physical arrangement of the logic units with respect to each other.
In accordance with one embodiment of the present invention, each modular logic array unit includes a generally circumferential border at which it is stitched onto any adjacent modular logic array unit.
Preferably the stitching is effected by removable conductive strips formed in a relatively high metal layer which are connected by vias to strips in a relatively lower metal layer, thereby to removably bridge gaps therebetween.
There is also provided in accordance with a preferred embodiment of the present invention an application specific integrated circuit (ASIC) including at least one modular logic array which is constructed of a plurality of modular logic array units physically arranged with respect to each other to define a desired aspect ratio.
Further in accordance with a preferred embodiment of the present invention each modular logic array unit includes a generally circumferential border at which it is stitched onto any adjacent modular logic array unit.
Still further in accordance with a preferred embodiment of the present invention adjacent modular logic array units display stitching at a common border thereof, the stitching being effected by removable conductive strips formed in a relatively high metal layer which are connected by vias to strips in a relatively lower metal layer, thereby to removably bridge gaps therebetween.
Additionally in accordance with a preferred embodiment of the present invention at least two adjacent modular logic array units are arranged to have their scan inputs and scan outputs in parallel. Alternatively or additionally at least two adjacent modular logic array units are arranged to have their scan inputs and scan outputs in series.
Moreover in accordance with a preferred embodiment of the present invention, the ASIC includes modular logic array units of at least two different geometrical configurations.
Preferably, each logic array unit includes between 10,000 and 200,000 gates.
Further in accordance with a preferred embodiment of the present invention each logic array unit has an area of between 0.5 square millimeter and 6 square millimeters.
Additionally in accordance with a preferred embodiment of the present invention each logic array unit has its own clock input and clock output. Furthermore each logic array unit has its own scan input and scan output.
There is also provided in accordance with yet another preferred embodiment of the present invention, a data file for an ASIC which includes at least a reference to a plurality of identical modular data files, each corresponding to a logic array unit and data determining the physical arrangement of the logic units with respect to each other.
Further in accordance with a preferred embodiment of the present invention each modular logic array unit includes a generally circumferential border at which it is stitched onto any adjacent modular logic array unit.
Still further in accordance with a preferred embodiment of the present invention adjacent modular logic array units display stitching at a common border thereof, the stitching being effected by removable conductive strips formed in a relatively high metal layer which are connected by vias to strips in a relatively lower metal layer, thereby to removably bridge gaps therebetween.
Additionally in accordance with a preferred embodiment of present invention at least two adjacent modular logic array units are arranged to have their scan inputs and scan outputs in parallel. Alternatively or additionally at least two adjacent modular logic array units are arranged to have their scan inputs and scan outputs in series.
Further in accordance with a preferred embodiment of the present invention, a data file which includes modular logic array units of at least two different geometrical configurations. Preferably each logic array unit comprises between 10,000 and 200,000 gates.
Moreover in accordance with a preferred embodiment of the present invention each logic array unit has an area of between 0.5 square millimeter and 6 square millimeters.
Still further in accordance with a preferred embodiment of the present invention each logic array unit has its own clock input and clock output.
Additionally each logic array unit has its own scan input and scan output.
There is also provided in accordance with yet another preferred embodiment of the present invention, a method for producing an ASIC including the steps of providing a plurality of modular logic array units physically arranged with respect to each other to define a desired aspect ratio.
Further in accordance with a preferred embodiment of the present invention each modular logic array unit includes a generally circumferential border at which it is stitched onto any adjacent modular logic array unit.
Still further in accordance with a preferred embodiment the present invention wherein adjacent modular logic array units are stitched at a common border thereof, stitching being effected by removable conductive strips formed in a relatively high metal layer which are connected by vias to strips in a relatively lower metal layer, thereby to removably bridge gaps therebetween.
Additionally in accordance with a preferred embodiment of the present invention at least two adjacent modular logic array units are arranged to have their scan inputs and scan outputs in parallel.
Furthermore at least two adjacent modular logic array units are arranged to have their scan inputs and scan outputs in series.
Moreover in accordance with a preferred embodiment of the present invention and including modular logic array units of at least two different geometrical configurations.
Still further in accordance with a preferred embodiment of the present invention each logic array unit comprises between 10,000 and 200,000 gates. Furthermore each logic array unit has an area of between 0.5 square millimeter and 2 square millimeters.
Further in accordance with a preferred embodiment of the present invention each logic array unit has its own clock input and clock output. Additionally each logic array unit has its own scan input and scan output.
There is provided in accordance with another preferred embodiment of the present invention a method of producing a data file for an ASIC which includes combining without compiling together a plurality of identical modular data files, each corresponding to a logic array unit and data determining the physical arrangement of the logic units with respect to each other.
Further in accordance with a preferred embodiment of the present invention each modular logic array unit includes a generally circumferential border at which it is stitched onto any adjacent modular logic array unit.
Still further in accordance with a preferred embodiment of the present invention a method of adjacent modular logic array units display stitching at a common border thereof, the stitching being effected by removable conductive strips formed in a relatively high metal layer which are connected by vias to strips in a relatively lower metal layer, thereby to removably bridge gaps therebetween.
Additionally in accordance with a preferred embodiment the present invention at least two adjacent modular logic array units are arranged to have their scan inputs and scan outputs in parallel. Furthermore at least two adjacent modular logic array units are arranged to have their scan inputs and scan outputs in series.
Moreover in accordance with a preferred embodiment of the present invention including modular logic array units of at least two different geometrical configurations.
Preferably each logic array unit comprises between 10,000 and 200,000 gates.
Additionally in accordance with a preferred embodiment of the present invention each logic array unit has an area of between 0.5 square millimeter and 6 square millimeters.
Still further in accordance with a preferred embodiment of the present invention each logic array unit has its own clock input and clock output. Additionally each logic array unit has its own scan input and scan output.
There is thus provided in accordance with a preferred embodiment of the invention a method of testing an integrated circuit comprising logic gates in the form of look up tables, wherein each logic table comprises at least two data bits, the method comprising modifying at least one of the data bits of one of the logic gates, and examining the effect of the modification on an output of the integrated circuit.
Further in accordance with a preferred embodiment of the present invention the logic gates are formed into groups within the integrated circuit, each group having at least two inputs and at least one output. Preferably the logic gates do not have independent inputs or independent outputs.
Additionally in accordance with a preferred embodiment of the present invention the modification is made into a high level language data file. Preferably the high level language data file is used to modify a second data file corresponding to the data bits of at least some of the logic gates. Additionally or alternatively the modified second data file as applied to at least some of the logic gates to modify at least some of the data bits thereof.
Moreover in accordance with a preferred embodiment of the present invention the step of selecting a modification of a given logic gate within a group to have the effect of neutralizing the effect of the given logic gate on an output of the group. Preferably the group is arranged as a flip-flop.
The present invention seeks to provide a method for automatic distribution and licensing of semiconductor device cores, particularly xe2x80x9chard coresxe2x80x9d as well as a modifiable core particularly suitable for use in the method.
There is thus provided in accordance with a preferred embodiment of the present invention a method for design and manufacture of semiconductors including producing a fab-ready design for a semiconductor device by importing into the design at least one core from a remote source, the core bearing an identification indicium, utilizing the fab-ready design to fabricate the semiconductor device and reading the identification indicium from the semiconductor device to indicate incorporation of the at least one core therein.
In accordance with a preferred embodiment of the present invention, there is provided a programmable or customizable core structure which can be incorporated in a design for a semiconductor device and which enables a user to assemble therewithin both conventional cores and programmable and customizable elements associatable therewith.
In accordance with a preferred embodiment of the present invention, the importing step includes communication of the core via a communications link, preferably the Internet.
Preferably, the reading step is associated with a reporting step which preferably includes reporting to an entity identified in the indicium the quantities and/or sizes of cores fabricated. This reporting step is preferably carried out by the fabrication facilities, preferably the foundry or mask shop as defined hereinbelow.
As the price of tooling and manufacturing such S.O.C""s is rapidly growing, and may be expected to exceed the $1 m mark for a 0.12 micron process, it is desirable to share and spread the costs of tooling amongst several customers.
Thus, in accordance with yet another preferred embodiment of the present invention, the method for designing and manufacturing semiconductors may also include the use of a company or body which provides the various services and resources required by a customer to design a required system on a chip.
In the present specification and claims, the company which provides this service is known as a xe2x80x9cVirtual ASICxe2x80x9d company.
An effective way for organizing this service is for the Virtual ASIC company to collate many different S.O.C. designs, which have been developed by other companies and include a wide range of previously built-in options. Each entry into the library or data bank, includes the S.O.C. identification in addition to the identification of the individual core included in it. The Virtual ASIC company would then store all the information in a data bank or library and make it available to different customers.
A customer wishing to design an S.O.C., chooses a device, from the data bank, which is similar to his design requirements. The customer finalizes his own S.O.C. design based on the device design and data stored in the library. A completed S.O.C. design bears the S.O.C. identification, in addition to the identification of the individual core included in it. On completing the design of the S.O.C., the customer may update the data bank held by the Virtual ASIC company with his S.O.C. design and data.
As described by the previous embodiments of the present invention, these design S.O.C.""s may include dedicated computerized functions, such as processors, DSP, and programmable and/or customizable logic.
Using different methods, such as known in the art computer codes, the Virtual ASIC company may calculate the costs for NRE and production which may result from the wafer costs, the royalty obligations to the various bodies which provided the cores, and to the S.O.C. integrator and the other service and customization charges.
Thus, the customer is now able to review the technical capabilities of the chip, the required NRE and the production costs of his design. If the all the requirements of the customer are fulfilled, the customer now go ahead and order the chip.
It is appreciated that such a service may be provided over the Internet to a customer who is interested to implement his own application based on the similar S.O.C. devices which are stored in the data bank of the Virtual ASIC.
The customer may include his own software code-for the processors and/or the DSP and to program and/or customize the logic to meet the customer""s own particular needs and requirements.